An accurate control of Phase Locked Loop (PLL) bandwidth is an important factor to optimize jitter performance in wireline and wireless communication systems. PCIe (Peripheral Components Interface Express) bus standard, for example, dictates a bandwidth range (e.g., 2 MHz to 5 MHz) for transmitter (Tx) PLLs and receiver (Rx) PLLs to address the tight jitter budget, and the standard also requires compliance tests for devices following the standard. Even when the PLL bandwidth is not specified by the standards, efficient system jitter budgeting can be performed through accurate bandwidth control, as such, filtering noise from each system component.
As process scales, however, PLL components are further affected by process, voltage, and temperature (PVT) variations, causing higher PLL bandwidth variation. To satisfy jitter performance and/or compliance with the standards, expensive tests and PLL bandwidth calibration techniques have been required.
The conventional off-chip bandwidth test with a signal generator is cost prohibitive for high volume manufacturing (HVM). Some solutions for addressing the problems associated with conventional off-chip bandwidth test are either measurement-only solutions or the interface for the calibration is still an analog component, which is vulnerable to another variation from the calibration steps. Also, analog PLL components (e.g. varactor) may suffer from process variations, so there may be yield concerns with or without performance of calibration steps.